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-- Full adder
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
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Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	-- latency 0 clk
entity FullAdder is

	port(
		a_in, b_in, c_in:in std_logic;
			add_out, c_out: out std_logic
	);
end entity;

architecture FullAdder of FullAdder is
begin

	c_out<=((c_in and a_in) or (c_in and b_in) or (a_in and b_in));
	add_out<=c_in xor a_in xor b_in;
	
end architecture;